SHIFT Smart High-Integration Flex Technologies: Thermal and mechanical modelling

Thermal and mechanical modelling and testing

Thermal modelling and measurement

The thermal performance of micro-electronic packages is usually expressed by the thermal resistance parameters Rth. Thermal resistance is defined as the change in temperature divided by the power dissipation that caused the temperature change for a steady start condition. While for the time-variant case, the term ‘thermal impedance’ Zth is often used instead, where Tjunction is the junction temperature of the chip, Tref is the reference temperature (e.g Tcold-plate, Tair , or Tfluid), and P is the heat dissipation of the chip.

The measurement of thermal resistance is possible if the power dissipation, the junction temperature on the chip, and the reference temperature are known.

A thermal test chip was designed for this purpose.It consists of a heat source and a temperature-sensing element. Two resistors on the thermal test chip are used to stimulate the heat dissipation. The measurement of the temperature is then realized by adding a small voltage and current across a diode. This forward voltage drop usually varies linearly with the temperature over a range suitable for making thermal resistance measurement, and it is very repeatable.

The first SHIFT thermal demonstrator uses a thermal test chip mounted on a flexible substrate by flip chip interconnection.

Both simulation and experimental measurements are employed in our work to quantity the thermal resistance. For the simulation, two different methods, Finite Element Method (FEM) and Computational Fluid Dynamics (CFD), are used. Rather than comparing the advantage of each method, our intention is to compensate and calibrate each other’s results. As a way to validate simulation results, experimental measurement is also done for steady state and transient thermal resistances.

A. FEM simulation - methods and results

FEM model

The FEM software is MSC Marc. Mentat. The model was constructed based on the real design dimensions. The chip has 5*5 mm2 square, is 0.7mm thick, with 92 solder joints connected to the flex substrate. Since the chip is not located at the centre, only one-fold symmetry along the vertical y-axis was exploited, thus the model could be reduced to one half of the entire structure. The overview of the model and the mesh details are viewed in Fig. 1. All joints are modeled because the connections from the chip to the substrate contribute the thermal performance. Copper tracks lead every three joints to the edge of the flex. The picture for cross section is illustrated in Fig. 2 with all the dimension details. A dielectric covering as solder mask is applied to define component placement areas.

One-watt heat dissipation is uniformly distributed over the active surface of the chip, which is a homogenous heat flux of 0.04W/mm2. Natural convection and cold-plate boundary conditions were separately applied. In the natural convection condition, all the surfaces that are exposed to the air have a heat transfer coefficient h=10 W/m2K. In the cold-plate boundary condition, the backside of the module was fixed at temperature 0°C. No natural convection was considered in this case because the chip was covered by foam for isolation in the real measurement condition.

The heat transfer coefficient is a parameter indicating how fast the heat is removed from the system by convection. The determination of the h value is a complicated task for a specific situation; it varies because of material, time, temperature difference, and normally it has a spatial distribution around the system. This uncertainty, however, is studied by a parameter study on h in the modelling. Reasonable values of h in our simulation range over about 6 orders of magnitude, from h=1 as perfect isolation to h=10000 as forced liquid convection. Five h values and four structures end up with 20 simulation cases.

To examine the thermal capabilities of multilayer flex, parameter study for the thermal conductivity of the substrate in out-of-plane direction was also studied.

FEM results

After applying a homogenous heat flux on the active surface of the chip, the resistance to the heat flux, which is related to the thermal conductivity of materials involved, results in significant internal heat generation. The heat flow is analogue to the electrical flow and moves along the path where the resistance is the smallest.

For the case without copper metallization a significant amount of heat is conducted through the copper tracks, while there is very limited heat spreading in the substrate. This conduction causes a very high temperature drop on the copper track, which is 396°C for the FC1 case. While for the case having copper at the backside majority of the heat was spreading into a larger area within metallization layer, even improving the efficiency of the heat absorption of the air. The thermal resistance in FC3 case turns out as 94K/W.

Under cold-plate boundary condition, on the other hand, heat conduction route is changed. The path from chip to joints, and then vertically through the substrate becomes the preferred way for heat; the temperature differences between the module and the cold-plate are the major driving force. Cold-plate is therefore dominating heat removal. Only a small heat spreading around the chip is observed in the copper metallization case, indicating copper metallization has a less pronounced effect than in natural convection condition.

B. CFD simulation - method and results

The applied simulation software was Flotherm, which is a commercial CFD tool based on Finite Volume method that solves airflow and heat transfer problems in and around electronic equipment.The tool solves the fully conjugated heat transfer problem: all three modes (conduction, convection, and radiation) are included. In practice, the 3-D Flotherm model is constructed much the same way as in any CAD tool.In addition, the parameters relevant for airflow and heat transfer are attached to each object. According to given initial and boundary conditions, the model solves Navier-Stokes equations by iterating in constructed computational grid.

Results can be presented for example as user-defined Monitor Point temperature readings (e.g. component junction temperature) or as false-colour views, where each colour on the surface represents the actual temperature at that point.

In order to study CFD modelling of flex structures and to provide reference data for FEM results, the basic multilayer flex structure was simulated. Material properties were needed. However, the in CFD separate generic heat transfer coefficient, h, does not need to be defined but the software automatically calculates the correct value for h at each surface point. Thus, no CFD simulations varying h were required.The temperature of ambient air was fixed to +20°C in all simulations. The obtained results were validated against performed experiments.

The computational domain in the CFD model must be considerably larger then the modeled object itself to correctly pick up the movement in the surrounding air. In the meshing, localized and nesting meshes were used to reduce total amount of grid points. The grid was denser where dimensions were small (flex thinness, traces, solder balls) or where thermally significant phenomena took place (active layer of die) and sparser at a less essential location (in-plane flex, surrounding air farther of the flex). The solution independency of grid density was verified by alternating the mesh.Compared to the final mesh, refined meshing did not change the temperature results.The entire number of grid points was 2.2 millions and a typical convergence time was about two hours.

The importance of copper traces and solder balls as heat conductors is clearly visible.

C. Conclusions

The measured and simulated thermal performance of the first SHIFT thermal demonstrator reveals that thin flex is a poor thermal conductor, while the key factor is the amount of coppers to remove heat over a larger area. The module without backside metallization has a significant amount of heat conduction through the copper tracks, while for the module having backside metallization, most of the heat transfer was the spreading into the substrate. Thermal resistance is also boundary-dependent: it is smaller at cold-plate condition, while 5-15 times higher at natural convection condition. The backside copper metallization plays an important role under natural convection condition, but not under cold-plate conditions.

Thermal resistance measurement

Experimental procedures

Measurements were performed on TRESIMEC, which is a computer controlled thermal resistance evaluation system. It was developed at IMEC to characterise the thermal performance of electronic packages in both steady state and transient mode.

The first step is the calibration. The test sample was immerged in a thermal bath filled with dielectric oil. The temperature of this thermal bath could be well controlled. The forward voltage drop of the diodes was measured within a temperature range, and then the relationship between voltage and temperature of the diode were recorded. This relationship was fitted into a linear equation for later measurement.

For natural convection, samples were placed in a JEDEC box emulating still air environment. For cold-plate condition, since the cold plate area is smaller than the sample, the surroundings of the chip were located on the cold plate, while rest of the sample was left in the air. The gap between the chip and the cold plate was filled with thermal gel to reduce the contact resistance, thus to make the heat transfer between substrate and cold plate as effective as possible. A black soap with soft pressure was applied on the chip top to isolate the heat removing from the chip directly to the air.

During the measurement, power was gradually applied until the temperature on the chip reached the maximum working temperature. Assumed power and increased temperature were recorded to calculate the thermal resistance. When the temperature responses are continually recorded within a short time interval for applied power, thermal impedance curve is obtained. Transient measurements are only completed for sample FC1 and FC4 under natural convection boundary conditions in our experiments.

An important feature of transient thermal impedance curve is that the first parts of all the curves overlap each other. These overlapped parts represent the temperature response when only the chip was heated up, so that neither packaging or copper or even boundary condition could have influenced it. These overlapped transient thermal impedance curve could be used to validate the material date we used for FEM. But since the shortest time interval we would achieve so far in measurement is 0.5s, the overlapped area is not accurate enough to make material validation.

Discussion

The thermal resistance is higher in natural convection condition than in cold-plate boundary condition, which means cold-plate boundary removes the heat more effectively than convection. Because of this difference, copper metallization at the backside plays different roles; it influences the final temperature on the chip much under natural convection condition, but not much under cold-plate condition.

Also, the more copper, the lower the temperature achieved on the chip. For example, as the thickness of copper track increases from 9 to 12mm, the temperature drop from 396°C in FC1 to 351°C in FC2 case.

As much slower, CFD reproduces reality more accurately than FEM, especially under natural convection. Indeed, it calculates the air flow and radiation much in detail, whereas FEM treats the convection coefficient as a homogeneous constant. On the other hand, FEM is quite good at heat conduction problems among solid materials, so it performs as well as CFD for the cold-plate case.

Moreover, resistance is a function of power in CFD. In natural convection case, power level is around 0.1 – 0.3 W, thus R might descend close to CFD. Larger power levels are needed. On the other hand, this is not a problem in FEM since only linear relationship is considered.

Conclusions

Mechanical and thermo-mechanical modelling

A. Mechanical modeling of ultra thin chip package (IMEC-Gent technology)

The FEM method has been used to calculate the stress induced in the test boards. The first part of the FEM simulation is the stress calculation after processing. Both the polymer and BCB are cured at 350°C, so the whole structure (excluding the copper metallisation) gets a cooling down from 350°C to 20°C. The silicon chip (169 GPa, 2.6 ppm/°C) and the polyimide (8.5 GPa, 3 ppm/°C) have almost the same coefficient of thermal expansion (CTE) so there will not be so much induced stress. However, the thin BCB (2.9 GPa, 42 ppm/°C) layer has a much higher CTE which will cause high tensile stresses in the BCB layer itself.

The second part of the FEM simulation is the mechanical bending of this UTCP. It is possible to manually bend this package with a curvature of about 5 mm damaging neither the silicon chip nor the BCB layer. For the silicon chip, the maximum allowable tensile stress is around 300 MPa. For BCB, the ultimate tensile stress is 87 MPa.

For the downward bending, a curvature of 5 mm is feasible, as it compensates the tensile stress in BCB by compressive stress. The stress in the silicon chip is in the neighbourhood the maximum allowable stress. For the upward bending, it is much more critical, as additional tensile stress in the BCB layer is induced due to the upward bending.

B. Thermo-mechanical modeling: component assembly on multilayer flex

The material property data: E, v, CTE of the board are predicted based on simulation on bending, uniaxial compression, and uniform heating up.

Approaches in thermo-mechanical analysis:

Build the FEA model of the package-board assembly;
Use the standardized cyclic temperature profile as thermal loading;
Identify the critical solder joint by running thermo-mechanical simulation with all the solder joints modeled with the same pattern of meshes;
Refine the meshes near the critical solder joint, and rerun the thermo-mechanical simulation;
Use simulation results to predict the solder fatigue life;
Verify the simulation results by experimental measurement data;

Standard temperature profile for thermo-cycling loading is shown in figure 4. The temperature range is from -40° C to 125° C. The ramping time is 11 to 16 minutes, while the dwelling time is 14 minutes.

To examine the simulation method, we assume the board thickness is 0.6mm; the material property data of the board are: E(young modulus)=6500MPa, v(poision ratio)=0.25, rho (mass density) =1.96e-3g/cm^3, CTE=26.1ppm. Further assumptions are made on the distribution of the packages on the board.

The solder fatigue life corresponding is calculated according ramping time of 3 and 11minutes respectively.

The solder fatigue life corresponding to ramping time of 11min is longer than that corresponding to ramping time of 3min.

C. Drop test analysis

Five different cases are to consider for drop test analysis.

Case 1: PWB parallel to the floor

Case 2: PWB perpendicular to and the long edge of PWB parallel to the floor

Case 3: PWB perpendicular to and the short edge of PWB parallel to the floor

Case 4: PWB parallel to the floor, but PWB is curved

Case 5: Based on Case 3, but PWB is curved

Some Results

According to simulation results, Case 1 is the most severe case. The peeling strain of solder in that case is the largest. This is due to the vibration of the board.
Among the 5 cases considered, Case 2 has the minimum solder peeling strain.
The solder peeling strain in Case 4 is a little less than that in Case 3.
Comparing Case 1 with Case 2 or Case 3, the solder peeling strain is much higher in Case 1 than in Case 2 or Case 3. This is because in Case 1 the board is bended and vibrates a lot.
Case 4 has less solder peeling strain than Case 1. The natural vibration behavior of the board changed from Case 1 to Case 4.

Snap shot of the displacement of curved PWB during the drop test with PWB parallel to the floor with different number of screw supports is simulated.

The PWB will deform and the upper part would hit the lower part. So Case 4 (screw support) is not safe for this kind of architecture.

Summary

With a board thickness of 0.6mm, the material property data of the board are taken as: E=6500MPa, v=0.25, rho (mass density) =1.96e-3g/cm^3, CTE=26.1ppm. Further assumptions are made on the distribution of the packages on the board. Drop tests with different board orientation and installation have been simulated for the purpose of drop test fixture design. Thermo-mechanical simulation with ramping time of 3 min and 11 min has been conducted to examine the effect of the ramping time on the solder fatigue life prediction. It is shown: the smaller the ramping time, the lower the solder fatigue life.